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Home > Products > eFPGA > ArcticPro

ArcticPro™ Ultra-Low Power Embedded FPGA (eFPGA) IP

Build Flexibility and Differentiation Into Your Next SoC

QuickLogic has been supplying FPGA-based products for consumer, industrial and mission-critical applications for nearly three decades. The company's embedded FPGA (eFPGA) initiative offers SoC designers the flexibility to easily implement post-production changes, thus providing the benefit of hardware programmability to their end customers. Multiple chip variants can be created from a single mask set, enabling customization to address fragmented and/or rapidly evolving standards.

Benefits - ArcticPro eFPGA:
  • Efficient Architecture: high logic cell utilization
  • Fine-Grain Architecture – can implement multiple input functions in two independent LUT3s or one LUT4
  • Up to 8:1 mux & independent 2:1 mux
  • Flexible Flip Flop
  • Flip flop can be driven by logic in the cell
  • Flip flop can be used independently of the logic in the cell
  • Highly Routable Architecture
  • Reduces routing delays
  • Multi-drop routing for better routing resource utilization
  • Array sizes ranging from 8x8 logic cells up to 64x64 logic cells

Product Options – 65nm

FoundryProcessDevice TypeArchitectureAvailable Array Sizes # of RAM bits# of Logic Cells# Flip Flop&&# GPIO
TSMC65nm LPSVTArcticPro32x3273,728 (RAMFIFO)10191019 (LC)
384 (IO)
128
GF65nm LPEHVT, SVTArcticPro32x3273,728 (RAMFIFO)
135,168 (ASSP)
10191019 (LC)
1019 (LC)
264 (IO)
88
Custom array sizes, process and device types available
&&22LC + PREIO register paths
**with die seal + scribe line

ArcticPro – 40nm

FoundryProcessMetal LayersAvailable Array Sizes# of Logic Cells# Flip Flop# Interface signals&&
GF40nm LP532x3210191019 (LC)
192 (IO)
64+768 (A2F%)
128+1536 (F2A%)
256 (DEF)
SMIC40nm LL532x3210191019 (LC)
192 (IO)
64+768 (A2F%)
128+1536 (F2A%)
256 (DEF)
TSMC40nm ULP532x3210191019 (LC)
192 (IO)
64+768 (A2F%)
128+1536 (F2A%)
256 (DEF)
Custom array sizes, process and device types available

Compiler Example Arrays

Available Array Sizes# of Logic Cells# Flip Flop&&# Interface signals&&
16x16251251 (LC)
96 (IO)
32+384 (A2F%)
64+768 (F2A%)
128 (DEF)
48x4822832283 (LC)
288 (IO)
96+1152 (A2F%)
192+2304 (F2A%)
384 (DEF)
&&LC + PREIO register paths
%(reg) + (combinatorial)
*Based on APB 40MHz clock